The present invention generally relates to semiconductor devices and methods of producing semiconductor devices, and more particularly to a semiconductor device which uses a compound semiconductor such as GaAs and a method of producing such a semiconductor device.
Compared to the metal oxide semiconductor (MOS) semiconductor devices which use silicon, the semiconductor device which uses a compound semiconductor can operate at a high speed and there is active research on the semiconductor device which uses the compound semiconductor. The aim of the research is to shorten the gate length so as to increase the operation speed and to reduce the size of elements so as to improve the integration density.
For a digital circuit which is formed in the semiconductor device which uses the compound semiconductor, a direct coupled field effect transistor logic (DCFL) circuit is generally used to improve the integration density. An inverter circuit which forms a basic circuit of the DCFL circuit is shown in FIG. 1.
The inverter circuit shown in FIG.1 includes an enhancement type FET 2 and a depletion type FET 4 which is connected to the FET 2 as a load. A source S of the FET 2 is grounded, and a drain D of the FET 2 is connected to a source S of the FET 4. A gate G of the FET 4 is connected to the source S of the FET 4, and a power source voltage V.sub.DD is applied to a drain D of the FET 4. An input signal V.sub.IN is applied to a gate G of the FET 2, and an output signal V.sub.OUT which is an inverted signal of the input signal V.sub.IN is output from a node which connects the drain D of the FET 2 and the source S of the FET 4.
FIGS. 2A and 2B show the conventional inverter circuit shown in FIG.1 with shortened gate length for the purpose of increasing the operation speed. FIG. 2A is a plan view of the conventional inverter circuit, and FIG. 2B is a cross sectional view along a line A-A' in FIG. 2A.
In FIG. 2B, an intrinsic GaAs buffer layer 12 is formed on a semiinsulative GaAs substrate 10, and an n-type GaAs active layer 14 is formed on the intrinsic GaAs buffer layer 12. An element forming region is defined by an isolation region 16 which is formed by implanting oxygen ions. A source electrode 18, a common electrode 19 and a drain electrode 20 are formed on the n-type active layer 14. A gate electrode 22 of the enhancement type FET 2 is formed between the source electrode 18 and the common electrode 19, and a gate electrode 23 of the depletion type FET 4 is formed between the common electrode 19 and the drain electrode 20. The common electrode 19 is used as a drain electrode of the FET 2 and also as a source electrode of the FET 4.
The lower portions of the gate electrodes 22 and 23 have a recess structure in the n-type GaAs active layer 14. The recess of the gate electrode 22 is slightly deeper than the recess of the gate electrode 23.
In the conventional inverter circuit, the gate electrodes 22 and 23 are made narrow and the cross sectional areas thereof are small so as to shorten the gate length. On the other hand, in the DCFL circuit which can realize the high-speed operation and high integration density, a relatively large current flows at the gate electrode 22. For this reason, the current density of the current flowing through the gate electrode 22 becomes extremely large when increasing the operation speed, and there is a problem in that the reliability of the element becomes poor.
In addition, as may be seen from FIG. 2A, various measures must be taken to input the input signal V.sub.IN to the conventional inverter circuit. Such measures include extending the gate electrode 22 of the FET 2 outside the element forming region and forming a contact hole in the extended portion, providing an interconnection layer 24 outside the element forming region to connect the gate electrode 23 of the FET 4 and the common electrode 19, and forming a contact hole in the interconnection layer 24 for outputting the output signal V.sub.OUT. Hence, the conventional inverter circuit requires a region outside the element forming region for providing contact holes and interconnections, and there is a problem in that it is difficult to improve the integration density.